1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a word line driver and a semiconductor memory device having the same for boosting an internal power supply voltage to a boosted voltage.
2. Description of the Related Art
In general, memory cells within a semiconductor memory device include an n-type metal-oxide-semiconductor (NMOS) transistor. Since the transistor has a leakage current component, the semiconductor memory device should periodically repeat a data recovery operation before data stored in a memory cell is erased due to the leakage current.
The data recovery operation is called a refresh operation and is performed in memory cells capable of being selected by dividing internal addresses in the semiconductor memory device. When an internal address is sequentially incremented, the data recovery operation is called a self-refresh operation.
When the address is sequentially incremented in the self-refresh operation, a word line connected to a gate terminal of an NMOS transistor within a memory cell is enabled, and hence data of the memory cell is recovered.
At this time, the NMOS transistor is turned on when a gate voltage is a threshold voltage Vt higher than a source voltage. Since a maximum voltage applied to the semiconductor memory device is an external power supply voltage VDD, a transferred voltage has a value (VDD−Vt) by threshold voltage drop.
In order to offset the effect of threshold voltage drop, the voltage of the word line uses a boosted voltage VPP (for example, 3.0 V) generated by boosting an internal power supply voltage VINT (for example, 1.5 V).
Since the boosted voltage VPP can compensate for threshold voltage loss, it is widely used in a dynamic random access memory (DRAM) circuit. A memory cell transistor has a minimum size among transistors configuring a chip. Since the memory cell transistor is a threshold voltage higher than other transistors, the amplitude of the boosted voltage VPP should be equal to or greater than a value (VDD+Vt) in a word line driver circuit.
However, in the boosted voltage generator for boosting the internal power supply voltage VINT to the boosted voltage VPP, there is a predetermined amount of current component consumed due to limited efficiency of the boosted voltage generator itself in a conventional charge pumping process.
FIG. 1 is a block diagram of a portion of a semiconductor memory device showing an operation in which a word line of the semiconductor memory device is enabled. The semiconductor memory device includes a boosted voltage generator 10, a command decoder 15, a row decoder 20, a row address predecoder 30, a word line controller 40, and a conventional word line driver 50. Functions of blocks will be described with reference to FIG. 1.
The boosted voltage generator 10 generates a boosted voltage VPP by receiving an internal power supply voltage VINT and pumping electric charge until a predetermined target voltage is reached. The command decoder 15 generates an internal command signal Pself by receiving and decoding an external command CMD. The row decoder 20 generates a word line enable bar signal NWEiB for activating corresponding word lines in response to row address signals RA [i:0] of predetermined bits.
The row address predecoder 30 generates multiple decoded row address signals DRAij to be selectively enabled according to activation of the semiconductor memory device in response to address signals RA [2:1] of other bits except the predetermined bits. The word line controller 40 receives a decoded row address signal DRAij and generates word line enable control signals PXi and PXiB for controlling a word line WL to be enabled or disabled. The word line driver 50 receives the boosted voltage VPP from the boosted voltage generator 10 and enables the word line WL in response to the word line enable bar signal NWEiB and the word line enable control signals PXi and PXiB.
FIG. 2 is a circuit diagram of a conventional word line driver of the semiconductor memory device shown in FIG. 1, which includes two p-type metal-oxide-semiconductor (PMOS) transistors P1 and P2, two NMOS transistors N1 and N2, an operating mode selector 111, configured with an inverter IN1 and an OR gate, and a boosted voltage controller 120, configured with a NAND gate.
The first PMOS transistor P1 receives the boosted voltage VPP from the boosted voltage generator 10 through a source terminal, and transfers the boosted voltage VPP to a boost node NO1 in response to an inverted signal of the word line enable control signal PXi, which is a first control signal, applied to a gate terminal. The second PMOS transistor P2 receives the boosted voltage VPP from the first PMOS transistor P1 through a source terminal and enables a corresponding word line WL connected to an enable node N02 with the boosted voltage VPP in response to the word line enable bar signal NWEiB applied to a gate terminal.
The first NMOS transistor N1 and second NMOS transistor N2 each receives a ground voltage through a source terminal. NMOS transistor N1 transfers the ground voltage to the enable node NO2 in response to the word line enable bar signal NWEiB applied to a gate terminal, and NMOS transistor N2 disables the corresponding word line WL connected to the enable node N02 with the ground voltage in response to the word line enable control signal PXiB, which is a second control signal, applied to a gate terminal.
FIG. 3 is a timing diagram showing an operation of the conventional word line driver shown in FIG. 2, in which a word line is enabled. The operation includes the external command CMD, the word line enable control signal PXi, the internal command signal Pself, a boost node voltage signal PXiD, the word line enable bar signal NWEiB, the word line enable control signal PXiB, and a word line signal WL.
The external command CMD is used to load an external self-refresh command for periodically recovering data stored in memory cells, while sequentially incrementing an internal address. The external command CMD is shown as only the self-refresh command for convenience of explanation, although the external command CMD may be a command for performing a command operation other than a normal operation for performing a data read, a data write, an active operation, or the like of the semiconductor memory device.
When the row address predecoder 30 activates a corresponding word line WL while the word line enable control signal PXi is initially maintained at a low level, the word line enable control signal PXi transits to a high level at times T1 and T4. When other word lines are activated, the word line enable control signal PXi re-transits to the low level at times T2 and T6.
The self-refresh command is loaded to the external command CMD. The internal command signal Pself is initially maintained at the low level and then the internal command signal Pself transits to the high level at time T3.
The word line enable control signal PXi transits to the high level at times T1 and T4, and transits to the low level at times T2 and T6, while the boost node voltage signal PXiD is initially maintained at the low level. The boost node voltage signal PXiD then transits to the boosted voltage VPP and the ground voltage VSS, respectively.
After a corresponding word line WL is disabled while the word line enable bar signal NWviB is initially maintained at the high level, the word line enable bar signal NWEiB transits to the low level at times T1 and T4 when the row decoder 20 activates the corresponding word line WL, such that the corresponding word line WL is enabled.
After the corresponding word line WL is disabled to the ground voltage while the word line enable control signal PXiB is initially maintained at the high level, the word line enable control signal PXiB transits to the low level at times T1 and T4 when the row address predecoder 30 activates the corresponding word line WL. When other word lines are activated, the word line enable control signal PXiB re-transits to the high level at times T2 and T6 and the corresponding word line WL is disabled to the ground voltage.
When the row decoder 20 activates the corresponding word line WL and the word line enable bar signal NWEiB transits to the low level at times T1 and T4 while the word line signal WL is initially maintained at the ground voltage VSS in response to the word line enable control signal PXiB, the boost node voltage signal PXiD is delayed for a given time and transferred. When other word lines are activated and the word line enable bar signal NWEiB transits to the high level at times T2 and T6, the word line signal WL is dropped to the ground voltage VSS in response to the word line enable control signal PXiB.
An illustrative operation in which a word line of the word line driver 50 is conventionally enabled will be described with reference to FIGS. 1 to 3.
Before a corresponding word line WL is activated at an initial time, the corresponding word line WL is deactivated when the corresponding word line enable bar signal NWEiB is deactivated to the high level and the corresponding word line enable control signals PXi and PXiB are deactivated to the low level and the high level, respectively. Accordingly, the corresponding word line enable control signal PXi at the low level is inverted to the high level by the NAND gate and is applied to the gate terminal of the first PMOS transistor P1. Then, the first PMOS transistor P1 is turned off and the supply of the boosted voltage VPP is interrupted. The second NMOS transistor N2 is turned on, the ground voltage is transferred to the enable node N02, and the corresponding word line WL is maintained at the ground voltage VSS.
First, an operation in which a word line of the semiconductor memory device is conventionally enabled in a normal operating mode will be described.
When a corresponding word line WL is activated in response to a corresponding row address signal among multiple row address signals in the row decoder 20, a corresponding word line enable bar signal NWEiB is activated to the low level at time T1 and corresponding word line enable control signals PXi and PXiB are activated to the high level and the low level, respectively.
When the corresponding row address signal is activated in the row decoder 20 and the internal command signal Pself indicating a self-refresh operation is applied at the low level, the internal command signal Pself is inverted to the high level by the inverter IN1 and is applied to an OR gate 121 along with the corresponding word line enable control signal PXi activated to the high level. The OR gate 121 outputs a high-level signal by performing an OR operation.
The NAND gate outputs a low-level signal by performing a NAND operation on the high-level signal output from the OR gate and the corresponding word line enable control signal PXi activated to the high level. The low-level signal is applied to the gate terminal of the first PMOS transistor P1. Accordingly, when the first PMOS transistor P1 is turned on, the boosted voltage VPP is transferred to the boost node NO1, and when the corresponding word line enable bar signal NWEiB is activated to the low level at time T1, the second PMOS transistor P2 is turned on, and the boosted voltage VPP is transferred to the enable node N02, such that the corresponding word line WL is enabled to the boosted voltage VPP.
Then, when other word lines are activated among multiple row address signals in the row decoder 20, the corresponding word line enable bar signal NWEiB is deactivated to the high level at time T2. The corresponding word line enable control signals PXi and PXiB are deactivated to the low level and the high level, respectively.
Accordingly, the corresponding word line enable control signal PXi at the low level is inverted to the high level by the NAND gate, and is applied to the gate terminal of the first PMOS transistor P1. Simultaneously, the corresponding word line enable control signal PXiB at the high level is applied to the gate terminal of the second NMOS transistor N2. At this time, the first PMOS transistor P1 is turned off to stop the transfer of the boosted voltage VPP to the boost node NO1, and the second NMOS transistor N2 is turned on to transfer the ground voltage to the corresponding word line WL, such that the word line WL is disabled.
Next, an operation in which a word line of the semiconductor memory device is conventionally enabled in the self-refresh operating mode will be described.
When a corresponding row address signal is activated in the row decoder 20 and the internal command signal Pself indicating the self-refresh operation is applied at the high level, the internal command signal Pself is inverted to the low level by the inverter IN1 and is applied to the OR gate, along with the corresponding word line enable control signal PXi activated to the high level. The OR gate outputs a high-level signal by performing an OR operation.
The NAND gate outputs a low-level signal by performing a NAND operation on the high-level signal output by the OR operation and the corresponding word line enable control signal PXi activated to the high level. The low-level signal of the NAND gate is applied to the gate terminal of the first PMOS transistor P1.
Accordingly, when the first PMOS transistor P1 is turned on, the boosted voltage VPP is transferred to the boost node NO1, and the corresponding word line enable bar signal NWEiB is activated to the low level at time T4. The second PMOS transistor P2 is turned on and the boosted voltage VPP is transferred to the enable node N02, such that the corresponding word line WL is enabled to the boosted voltage VPP.
Then, when other word lines are activated among multiple row address signals in the row decoder 20, the corresponding word line enable bar signal NWEiB is deactivated to the high level at time T6. The corresponding word line enable control signals PXi and PXiB are deactivated to the low level and the high level, respectively.
Accordingly, the corresponding word line enable control signal PXiB at the high level is applied to the gate terminal of the second NMOS transistor N2. The second NMOS transistor N2 is turned on and the ground voltage is transferred to the corresponding word line WL, such that the corresponding word line WL is disabled.
In the conventional word line driver 50 of the semiconductor memory device, the corresponding word line WL is enabled and corresponding memory cell data coupled to the word line are recovered. In the case of both the normal operating mode and the self-refresh operating mode, the voltage of the enabled word line WL becomes the boosted voltage VPP.
At this time, a fixed amount of boosted voltage charge is additionally consumed due to limited efficiency of the boosted voltage generator 10 within the semiconductor memory device. That is, the boosted voltage generator 10 receives the internal power supply voltage VINT and the boosted voltage charge is supplied through the charge pumping process. The boosted voltage generator 10 may have a predetermined efficiency limit since the boosted voltage VPP of 100% is not generated while consuming the entire internal power supply VINT.
For example, an internal power supply current of about 30 mA is consumed to supply a boosted current of 10 mA. In this case, the boosted voltage generator 10 has an efficiency of about 33% (=(10 mA/30 mA)*100). Accordingly, although the internal power supply current to be actually consumed is only 10 mA, an additional internal power supply current of 20 mA is inefficiently consumed to generate the boosted current of 10 mA.